The present invention relates to nonvolatile memories.
FIGS. 1-4 illustrate a flash memory fabrication process described in van Duuren et al., “Compact poly-CMP embedded flash memory cells for one or two bit storage”, Proceedings of NVSMW 2003 (Non-Volatile Semiconductor Memory Workshop), Monterey, Calif., pages 73-74. Tunnel oxide 150, polysilicon floating gate 160, inter-poly dielectric 164, control gate 170, and a nitride cap layer 172 are fabricated in a stacked structure (“FG/CG stack”). TEOS spacers 176 are formed on both sides of the stack. Then oxide 130 is grown for the access gate.
AG (access gate) polysilicon 140 is deposited over the FG/CG stack. See FIG. 2. Polysilicon 140 is polished by chemical mechanical polishing (CMP), as shown in FIG. 3. Then polysilicon 140 is patterned using resist 173 to define the access gate, as shown in FIGS. 3 and 4. Source/drain regions 174 are formed to obtain a one-bit memory cell 102 (FIG. 4).
As noted in the Duuren et al. article, the length of access gate 140 depends on the mask alignment, “which could lead to an odd-even word line effect in arrays”.
FIG. 5 shows a two-bit memory cell 110 described in the same article. Two FG/CG stack transistors 110L, 110R share an access gate 140. According to the Duuren et al. article, the cell is fabricated with the same process as cell 102, but cell 110 is fully self-aligned and therefore not sensitive to mask misalignment.
Each bit 110L, 110R can be programmed or erased independently of the other bit. The bit can be programmed by Fowler-Nordheim tunneling (FN) or source side injection (SSI). The Duuren et al. article states that the two bit cell has been studied “with 180 bit arrays in a virtual ground configuration”. The read, program (SSI) and erase voltages bit 110R are shown respectively in FIGS. 6, 7 and 8. In the read and program operations (FIGS. 6 and 7), the “pass” voltage for the control gate in bit 110L (6.0 V) is high enough to turn on the corresponding FG/CG transistor regardless of the state of its floating gate.
In order to reduce the memory operating voltages, it is desirable to increase the “gate coupling ratio”, i.e. the ratio of the capacitance between the floating and control gates to the capacitance between the floating gate and the substrate or other elements of the integrated circuit.